1. Field of the Invention
The present invention relates to the field of circuit testing, and more particularly to the test patterns used by a built-in self-test (BIST) routine in a microprocessor.
2. Prior Art
Conventional methods for testing digital logic circuit boards have become steadily less effective as integrated circuits mounted on the boards have both shrunk in size and grown in complexity. Test techniques that became popular in the 1980s, notably in-circuit testing, depend on the ability to make contact with circuit connections internal to a loaded board. Such techniques include the use of hand-held diagnostic probes and so-called "bed-of-nails" fixtures. Unfortunately, these techniques are difficult to implement in the face of the high board density of surface-mounted devices, particularly when applied to double-sided boards.
One technique, functional testing, relies primarily on stimulating a loaded board at its input and observing its output. As integrated circuits become more complex, it becomes more difficult to generate tests that will exercise them fully from the board edge connector that serves as the input for the test. Test data must propagate through a number of complex chips to reach those only remotely coupled to the input. As a consequence, long test sequences are required to reach these remote chips, making functional testing not optimally effective.
Similarly, as integrated circuits become more complex, it becomes more difficult to test units within the integrated circuit itself by applying signals from the external IC pins. The bottom line is that, with respect to both circuit boards and the ICs themselves, increasing amounts of circuitry must be tested through a relatively constant number of external interfaces.
To address this problem, manufacturers have incorporated IEEE standard test access ports (TAP) into their chips. The TAP is used for boundary-scan testing in which a shift register path is incorporated into an IC between each pin and the logic inside the chip. This technique permits test patterns to be shifted in through the input pins of the chip, and the state of the chip in response to the input to be observed at the output pins in a single-step mode. When the IC is put into test mode, the data loaded into the shift register cells is used instead of the data flowing to or from the pins, so that either the internal chip logic or the external chip-to-chip connections can be tested.
Although the boundary-scan technique provides access to the input and output pins of an IC, the technique does not permit any access to the complex internal units of the chip. Accordingly, manufacturers have incorporated test equipment for executing a built-in self-test (BIST) directly into the loaded boards and the circuits. This built-in test equipment may be directly integrated into the hardware of the functional units to be tested, or encoded into microcode ROM. The BIST routine can be invoked by asserting a Self-Test pin on the processor or by using a JTAG test access port (IEEE Std 1149.1) to load a RUNBIST instruction to execute the BIST routine.
In a simple implementation, the output of the BIST test is interfaced to the external world through a BIST FAIL pin. In an enhanced implementation, when a circuit fails the BIST, a fail message indicating which functional units failed the test is stored in the processor register file. For further information on BIST for RAM and TAP, please refer to V. C. Alves, M. Nicolaidis, P. Lestrat, B. Courtois, "Built-In Self-Test for Multi-Port RAMs," 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers (91CH3026-2), 248-251; C. M. Maunder, R. E. Tulloss, "Testability on TAP," IEEE Spectrum, 34-37 (February 1992).
A number of faults can lead to circuit failure. Some of the more common faults tested by the BIST include the following:
1. Memory cells stuck at 1/0 fault. PA1 2. Memory cell state transition 1-to-0 and 0-to-1 fault. PA1 3. Inter-cell interference (state coupling or cross talk). PA1 4. Multiple access or wrong addressing faults in the decoder. PA1 5. Data retention fault.
As a particular example, the first fault occurs when a memory cell is stuck at one or zero, and does not toggle in accordance with its data input. As another example, cross talk occurs when the state of one cell affects the state of a neighboring cell.
To test these faults, because BIST testing is rather lengthy, manufacturers have incorporated a number of compromises into their BIST implementations. For example, in conventional processors, the BIST routine uses predetermined or randomly generated patterns to fill and test the CPU hardware units, such as the cache. The predetermined test pattern is designed to match only the most common fault models. A drawback of the predetermined pattern approach is that it is designed under the assumption that all memory devices tested by the BIST follow the same memory cell layout. Unfortunately, the relationship between the memory device address lines and the physical location of the memory cells may change. For example, a predetermined test pattern of alternating ones and zeros may be used to detect cross talk (i.e., whether the cells excited by a one data bit affect the state of neighboring cells receiving a zero bit.). This test is effective if sequentially addressed cells are sequentially laid out in the physical chip according to the same sequence. However, if, for example, odd-addressed cells are physically grouped together in one location and even-addressed cells are physically grouped together in another location, then the alternating pattern will not provide an effective test for inter-cell interference.
The random generated pattern is not directed to implementing a particular fault model, but rather is used to obtain a statistical determination of the chip failure rate. One drawback of the random pattern method is that it must be run a number of times to ensure a satisfactory level of statistical certainty as to the accuracy of the test.
A disadvantage of both the predetermined and randomly generated test patterns is that the user has no control over the test pattern used by the BIST routine. As described above, the user can only invoke the BIST program and observe whether the circuit passed or failed, with little additional information provided. In a number of instances, however, the user may desire to modify the test pattern. For example, if the cell layout of a memory device to be tested does not conform to the test pattern embedded in the BIST program, then the user must be able to modify the test pattern applied to the memory cells. Further, the use of unmodifiable patterns prevents the user from pinpointing a particular memory cell causing chip failure.
In the recent past, the size of on-chip memory was relatively small. As a result, a test pattern implementing the most common fault models was highly likely to catch circuit defects. If an error was detected, the chip was simple thrown away. As on-chip memory size and density have increased, however, the need for more sophisticated testing has arisen. For example, the increase in memory capacity also increases the likelihood that relatively uncommon problems (that are not detectable by common fault models) may give rise to chip failure. Thus, a BIST routine based upon a common fault model may not detect a defective chip. In addition to this purely statistical reason for an increase in the relatively less common defects, the increase in circuit density has resulted in extremely fine submicron line spacing, which physically increases the risk of certain faults. A user who is suspicious that a circuit may be exhibiting an uncommon fault would not have the ability to select an appropriate test pattern under the current BIST implementation.
Thus, it can be appreciated that more flexibility in test pattern selection is desired. By allowing the user to modify the test pattern, the user would be able to account for changes in memory cell layout, detect relatively uncommon faults, and pinpoint the location of certain errors. By pinpointing a defective cell in a cache, for example, the user can simply "lock out" the defective portion of the cache, thus avoiding the need to scrap the circuit by accepting a smaller capacity chip.